semiconductor technical data order this document by MPC954/d 1 rev 1 ? motorola, inc. 2000 06/00 the MPC954 is a 3.3v compatible, pll based zero delay buffer targeted for high performance clock tree designs. with 11 outputs at frequencies of up to 100mhz and output skews of 200ps the MPC954 is ideal for the most demanding clock tree designs. the devices employ a fully differential pll design to minimize cycletocycle and phase jitter. ? fully integrated pll ? output frequency up to 100mhz ? outputs disable in high impedance ? tssop packaging ? 50ps cycletocycle jitter typical the analog v cc pin of the device also serves as a pll bypass select pin. when driven low the v cca pin will route the ref_clk input around the pll directly to the outputs. the oe input is a logic enable for all of the outputs except qfb. a low on the oe pin forces q0q9 to a logic low state. the MPC954 is fully 3.3v compatible and requires no external loop filter components. all inputs accept lvcmos or lvttl compatible levels while the outputs provide lvcmos levels with the ability to drive terminated 50 w transmission lines. the output impedance of the MPC954 is 10 , therefore for series terminated 50 w lines, each of the MPC954 outputs can drive two traces giving the device an effective fanout of 1:22. the device is packaged in a 24lead tssop package to provide the optimum combination of board density and performance. figure 1. block diagram ref_clk fb_clk pll v cca q0 q9 qfb oe (int pull down) (int pull down) low voltage pll zero delay buffer dt suffix 24lead tssop package case 948h01
MPC954 motorola timing solutions 2 agnd vcc q0 q1 q2 gnd q3 ref_clk vcca vcc q9 q8 gnd MPC954 function tables v cca function 1 0 pll enabled pll bypass oe function 1 0 q0 q9 enabled q0 q9 low figure 2. 24lead pinout (top view) q4 vcc qfb q6 q5 gnd gnd q7 oe vcc fb_clk 124 223 322 421 520 619 718 817 916 10 15 11 14 12 13 absolute maximum ratings* symbol parameter min max unit v cc supply voltage 0.3 4.6 v v i input voltage 0.3 v cc + 0.3 v i in input current 20 ma t stor storage temperature range 40 125 c * absolute maximum continuous ratings are those values beyond which damage to the device may occur. exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. functional operation under absolutemaximumrated co nditions is not implied. thermal characteristics proper thermal management is critical for reliable system operation. this is especially true for high fanout and high drive capability products. generic thermal information is available for the motorola clock driver products. the means of calculating die power, the corresponding die temperature and the relationship to longterm reliability is addressed in the motorola application note an1545.
MPC954 eclinps and eclinps lite dl140 e rev 3 3 motorola dc characteristics (t a = 0 to 70 c, v cc = 3.3v 5%) symbol characteristic min typ max unit condition v ih input high voltage lvcmos inputs 2.0 3.6 v v il input low voltage lvcmos inputs 0.8 v v oh output high voltage 2.4 v i oh = 20ma, note 1. v ol output low voltage 0.5 v i ol = 20ma, note 1. i in input current 120 m a note 2. c in input capacitance 4 pf c pd power dissipation capacitance 25 pf per output i cc maximum quiescent supply current 40 ma all vcc pins i ccpll maximum pll supply current 15 ma vcca pin only 1. the MPC954 outputs can drive series or parallel terminated 50 w (or 50 w to v cc /2) transmission lines on the incident edge (see applications info section). 2. inputs have pullup resistor which affect input current. pll input reference characteristics (t a = 0 to 70 c) symbol characteristic min max unit condition f ref reference input frequency 50 100 mhz f refdc reference input duty cycle 25 75 % ac characteristics (t a = 0 c to 70 c, v cc = 3.3v 5% ) symbol characteristic min typ max unit condition t r , t f output rise/fall time 0.3 1.5 ns 0.8 to 2.0v, (note 3.) t pw output duty cycle 40 50 60 % (note 3.) t sk(o) outputtooutput skews 300 ps (note 3.) f max maximum output frequency pll mode 50 100 mhz (note 3.) t pd (lock) ref_clk to fb_clk delay (with pll locked) 300 0 ps (note 3.) t plz , hz output disable time 7 ns (note 3.) t pzl output enable time 7 ns (note 3.) t jitter cycletocycle jitter (peaktopeak) 50 ps (note 3.) t lock maximum pll lock time 10 ms 3. termination of 50 to v cc /2.
MPC954 motorola timing solutions 4 power supply filtering the MPC954 is a mixed analog/digital product and as such it exhibits some sensitivities that would not necessarily be seen on a fully digital product. analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. the MPC954 provides separate power supplies for the output buffers (vcco) and the phaselocked loop (vcca) of the device. the purpose of this design technique is to try and isolate the high switching noise digital outputs from the relatively sensitive internal analog phaselocked loop. in a controlled environment such as an evaluation board this level of isolation is sufficient. however, in a digital system environment where it is more difficult to minimize noise on the power supplies a second level of isolation may be required. the simplest form of isolation is a power supply filter on the vcca pin for the MPC954. figure 3 illustrates a typical power supply filter scheme. the MPC954 is most susceptible to noise with spectral content in the 1khz to 10mhz range. therefore the filter should be designed to target this range. the key parameter that needs to be met in the final filter design is the dc voltage drop that will be seen between the v cc supply and the vcca pin of the MPC954. from the data sheet the i vcca current (the current sourced through the vcca pin) is typically 15ma (20ma maximum), assuming that a minimum of 3.0v must be maintained on the vcca pin very little dc voltage drop can be tolerated when a 3.3v v cc supply is used. the resistor shown in figure 3 must have a resistance of 1015 w to meet the voltage drop criteria. the rc filter pictured will provide a broadband filter with approximately 100:1 attenuation for noise whose spectral content is above 20khz. as the noise frequency crosses the series resonant point of an individual capacitor it's overall impedance begins to look inductive and thus increases with increasing frequency. the parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the pll. it is recommended that the user start with an 810 w resistor to avoid potential v cc drop problems and only move to the higher value resistors when a higher level of attenuation is shown to be needed. figure 3. power supply filter vcca vcc MPC954 0.01 m f 22 m f 0.01 m f 3.3v r s =515 w although the MPC954 has several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential pll) there still may be applications in which overall performance is being degraded due to system power supply noise. the power supply filter schemes discussed in this section should be adequate to eliminate power supply noise related problems in most designs. driving transmission lines the MPC954 clock driver was designed to drive high speed signals in a terminated transmission line environment. to provide the optimum flexibility to the user the output drivers were designed to exhibit the lowest impedance possible. with an output impedance of approximately 10 w the drivers can drive either parallel or series terminated transmission lines. for more information on transmission lines the reader is referred to application note an1091 in the timing solutions brochure (br1333/d). in most high performance clock networks pointtopoint distribution of signals is the method of choice. in a pointtopoint scheme either series terminated or parallel terminated transmission lines can be used. the parallel technique terminates the signal at the end of the line with a 50 w resistance to vcc/2. this technique draws a fairly high level of dc current and thus only a single terminated line can be driven by each output of the MPC954 clock driver. for the series terminated case however there is no dc current draw, thus the outputs can drive multiple series terminated lines. figure 4 i llustrates an output driving a single series terminated line vs two series terminated lines in parallel. when taken to its extreme the fanout of the MPC954 clock driver is effectively doubled due to its capability to drive multiple lines. figure 4. single versus dual transmission lines 7 w in MPC954 output buffer r s = 43 w z o = 50 w outa 7 w in MPC954 output buffer r s = 36 w z o = 50 w outb0 r s = 36 w z o = 50 w outb1 the waveform plots of figure 5 show the simulation results of an output driving a single line vs two lines. in both cases the drive capability of the MPC954 output buffers is more than sufficient to drive 50 w transmission lines on the incident edge. note from the delay measurements in the simulations a delta of only 43ps exists between the two differently loaded outputs. this suggests that the dual line driving need not be used exclusively to maintain the tight outputtooutput skew of the MPC954. the output waveform in figure 5 shows a step in the waveform, this step is caused
MPC954 eclinps and eclinps lite dl140 e rev 3 5 motorola by the impedance mismatch seen looking into the driver. the parallel combination of the 43 w series resistor plus the output impedance does not match the parallel combination of the line impedances. the voltage wave launched down the two lines will equal: vl = vs ( zo / (rs + ro +zo)) zo = 50 w || 50 w rs = 43 w || 43 w ro = 7 w vl = 3.0 (25 / (21.5 + 7 + 25) = 3.0 (25 / 53.5) = 1.40v at the load end the voltage will double, due to the near unity reflection coefficient, to 2.80v. it will then increment towards the quiescent 3.0v in steps separated by one round trip delay (in this case 4.0ns). figure 5. single versus dual waveforms time (ns) voltage (v) 3.0 2.5 2.0 1.5 1.0 0.5 0 2 4 6 8 10 12 14 outb t d = 3.9386 outa t d = 3.8956 in since this step is well above the threshold region it will not cause any false clock triggering, however designers may be uncomfortable with unwanted reflections on the line. to better match the impedances when driving multiple lines the situation in figure 6 should be used. in this case the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched. figure 6. optimized dual line termination 7 w MPC954 output buffer r s = 22 w z o = 50 w r s = 22 w z o = 50 w 14 w + 22 w 22 w = 50 w 50 w 25 w = 25 w spice level output buffer models are available for engineers who want to simulate their specific interconnect schemes. in addition iv characteristics are in the process of being generated to support the other board level simulators in general use.
MPC954 motorola timing solutions 6 outline dimensions dt suffix tssop package case 948h01 issue o dim min max min max inches millimeters a 7.70 7.90 0.303 0.311 b 4.30 4.50 0.169 0.177 c 1.20 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.27 0.37 0.011 0.015 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash, protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane w. s u 0.15 (0.006) t 2x l/2 s u m 0.10 (0.004) v s t l u seating plane 0.10 (0.004) t ?? ?? section nn detail e j j1 k k1 detail e f m w 0.25 (0.010) 13 24 12 1 pin 1 ident. h g a d c b s u 0.15 (0.006) t v 24x ref k n n
MPC954 eclinps and eclinps lite dl140 e rev 3 7 motorola notes
MPC954 motorola timing solutions 8 motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, represe ntation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the applicati on or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. atypicalo para meters which may be provided in motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all ope rating parameters, including atypicalso must be validated for each customer application by customer's technical experts. motorola does not convey any license under it s patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical imp lant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product cou ld create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expens es, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized u se, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motoro la, inc. motorola, inc. is an equal opportunity/affirmative action employer. MPC954/d ? mfax is a trademark of motorola, inc. how to reach us: usa / europe / locations not listed : motorola literature distribution; japan : nippon motorola ltd.: spd, strategic planning office, 4321, p.o. box 5405, denver, colorado 80217. 13036752140 or 18004412447 nishigotanda, shinagawaku, tokyo 141, japan. 813548 78488 customer focus center: 18005216274 mfax ? : rmfax0@email.sps.mot.com touchtone 1 6022446609 asia / pacific : motorola semiconductors h.k. ltd.; 8b tai ping industrial park, motorola fax back system us & canada only 18007741848 51 ting kok road, tai po, n.t., hong kong. 85226629298 http://sps.motorola.com/mfax/ home page : http://motorola.com/sps/
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